1. Technical Field
The present invention relates generally to a very low power logic circuit family with enhanced noise immunity, and more particularly pertains to a very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity.
A growing list of applications require low power electronic circuits. Some applications are portable and battery power. Other examples include complex designs which have simply exceeded their power budget. Decreasing the power supply is perhaps the most effective way to reduce power dissipation. In CMOS circuits the power dissipated is very nearly proportional to the square of the power supply voltage. Simply reducing the voltage to a given logic circuit in a given technology, however, leads to two additional and undesired results. The circuits become slower and more sensitive to noise generated by external sources.
The present invention lowers power dissipation in a broad family of logic circuits while avoiding the two undesired results of the circuits becoming slower and more sensitive to noise generated by external sources.
2. Prior Art
FIG. 1 depicts a relevant prior art circuit developed by Knepper. In the 1970's Knepper developed a way to reduce logic voltage swings over logic networks while maintaining larger logic signal swings within the logic gates. The technology of choice at that time was Depletion Load NMOS; and the development was applied to improve performance, not to decrease power. FIG. 1 illustrates this prior art circuit having a single logic input signal to an input transistor 10, coupled to vdd or Vref, and a second transistor 12, coupled to Vdd, with an output to logic gates 14.
Two decades later Nakagome applied a similar technique in CMOS to decease the logic voltage swings on logic buses, this time to save power. FIG. 2 illustrates an exemplary circuit as developed by Nakagome to decrease the logic voltage swings on logic buses to save power, and comprising a bus driver circuit having a source offset driver (a) and an internal supply generator (b).
It is noted that both of the above described pieces of prior art are "single ended" not differential.